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Ebook Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, by David Chinnery, Kurt Keutzer
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by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy’s comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.
- Sales Rank: #3621424 in Books
- Published on: 2002-06-30
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x 1.00" w x 6.14" l, 1.65 pounds
- Binding: Hardcover
- 414 pages
Review
From the reviews:
"This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer."
(William J. Dally, Professor, Stanford University)
"Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close `the Gap Between ASIC and Custom'."
(Kees Vissers, Director of Architecture, Trimedia Technologies Inc.)
"This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies."
(Richard Goering, EDA Editorial Director, EE Times)
"I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets."
(Gary Smith, Chief Analyst, Dataquest)
"This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design."
(Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys)
"Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators of this millennium."
(Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)
Most helpful customer reviews
0 of 0 people found the following review helpful.
Shows the way.
By J. W. Byrn
This is a very useful book to help focus on how to develop high performance designs. It is a little dated on the technologies covered but gets the job done. One thing to remember is that microprocessor development methods usually will become ASIC development methods after a number of years and related EDA tool development.
5 of 5 people found the following review helpful.
A study of fast processor design
By Jonah Probell
Whether trying to maximize the speed of a standard cell ASIC processor design or minimize the design time of a full custom processor this book describes, in detail, the considerations involved. The authors draw on real-world designs and extensively review several in particular. The book describes the impact on resulting processor performance of pipeline depth, clock tree design, register and latch choice, setup and clock-to-q times, slack passing, dynamic logic, logic design style, richness of standard cell library, wire and transistor sizing, floorplanning and other layout concerns, and the exploitation of process variation.
This book focuses strictly on processor circuit design and does not discuss software design, instruction set architecture, or die size and power issues.
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