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Reuse Methodology Manual for System-on-a-Chip Designs, by Michael Keating, Pierre Bricaud
PDF Download Reuse Methodology Manual for System-on-a-Chip Designs, by Michael Keating, Pierre Bricaud
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Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come.
Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips.
In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality.
From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques. Features of the Third Edition:
- Up to date;
- State of the art;
- Reuse as a solution for circuit designers;
- A chronicle of "best practices";
- All chapters updated and revised;
- Generic guidelines - non tool specific;
- Emphasis on hard IP and physical design.
- Sales Rank: #3300067 in Books
- Published on: 2002-06-30
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x .81" w x 6.14" l, 1.43 pounds
- Binding: Hardcover
- 292 pages
Most helpful customer reviews
0 of 0 people found the following review helpful.
I am mapping STARC rules with the contents
By kaizen
I an using STARC RTL style design guide with this manual.
I am mapping STARC rules with the contents of follows.
5.2 Basic Coding Practices
5.2.1 General Naming Conventions
5.2.2 Naming Conventions for VITAL Support
5.2.3 State Variable Names
5.2.4 Include Informational Headers in Source Files
5.2.5 Use Comments
5.2.6 Keep Commands on Separate Lines
5.2.7 Line Length
5.2.8 Indentation
5.2.9 Do not use HDL Reserved Words.
5.2.10 Port Ordering
5.2.11 Port Maps and Generic Maps
5.2.12 VHDL Entity, Architecture and Configuration Section
5.2.13 Use functions
5.2.14 Use loops and arrays
5.2.15 use meaningful labels
5.3 Coding for Portability
5.4 Guidelines for Clocks and resets
These are very helpful with us.
2 of 3 people found the following review helpful.
Very useful in practice
By Lee,
This book pointed out many design problems that I just met before. Designer could avoid many of them by following the guidelines in this book. I think it would help me a lot in my design work. Thanks to the authors.
0 of 0 people found the following review helpful.
good book
By jambar4458
The book is is very good at what it is. I need a book to talk about reusing code this is the book.
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